This invention relates generally to semiconductor logic circuits and more particularly to the static current parametric testing of current steering logic circuits.
Static current testing of CMOS logic circuits has long been accepted as an effective parametric test for determining reliability problems in integrated circuits. This testing method begins by setting the circuit to a known static state and measuring the static current drawn by the device in this static state. If the measured leakage current exceeds a predetermined threshold level, the device is sorted out due to potential reliability problems. In a typical CMOS process, this threshold level is approximately 10-20 microamperes.
Due to the small value of the threshold level, static current testing requires that the device not consume any additional static current other than leakage currents. For typical CMOS circuits, this can be accomplished by simply disabling the clock signal during the test to eliminate any dynamic currents caused by the switching of the gates.
Where the device consumes a bias current under normal operating conditions, however, the device cannot be tested under these normal operating conditions because the bias current would need to be disabled. This effectively prevents whole families of circuits from being static current tested. For example, a logic circuit containing a constant current logic gate 30 shown in FIG. 3 or a folded source coupled logic gate 35 shown in FIG. 4 would be precluded from using static current testing due to the bias current consumed during normal operation. Constant current logic has several key advantages over typical CMOS, however, which make it more desirable in certain applications than typical CMOS.
Constant current logic minimizes one of the fundamental problems of typical CMOS logic circuits-electromagnetic interference (EMI). For example, referring to FIG. 1, a CMOS inverter 10 exhibits a current spike when the conduction regions of P-channel field effect transistor (FET) 14 and N-channel FET 12 overlap. The current spike occurs when input voltage V.sub.IN, as seen at the gates of FET 12 and FET 14, is approximately equal to the threshold voltage V.sub.T. The input voltage V.sub.IN, and corresponding output voltage V.sub.OUT, are shown in FIG. 2A. The corresponding current spike is shown in FIG. 2B.
As a consequence of this current spike, and others like it through out a logic circuit, two undesirable effects occur. The first is that the noise induced by the switching is coupled directly into the substrate and will couple into analog blocks on the same chip and thereby severely degrade the performance of the analog blocks. The second effect, and a potentially more detrimental one, is the electro-magnetic interference ("EMI") generated by the current spikes.
In many applications, a power supplying conductor, which supplies the logic gates with current, is routed across either a chip or a printed circuit board over a fairly large distance. The conductor (not shown) will have a finite inductance which is directly proportional to the length of the conductor. A current passing through an inductor produces a change in voltage dV according to the commonly know expression shown below: EQU dV=L.times.(dI/dT),
where L represents the inductance of the inductor and dI represents the change in the current over the a corresponding change in time dT, as shown in FIG. 2B. The corresponding change in voltage dV is then radiated away from the power conductor with the power conductor acting as an antenna. This produces undesirable levels of EMI.
The constant current logic gate 30 shown in FIG. 3, for applications that do not require a low power circuit, can be used to virtually eliminate the current spike. The constant current logic gate 30 includes of a first P-channel current source transistor MP1 having a source connected to a supply terminal 22 for receiving a supply voltage V.sub.DD, a gate 24 for receiving a predetermined bias voltage V.sub.BIAS, and a drain. The P-channel transistor MP1 acts as a constant current source with the bias voltage biasing the transistor to conduct a predetermined amount of constant current. The constant current logic gate 30 also includes of a first N-channel transistor MN1 having a drain connected to the drain of the P-channel transistor MP1, a source coupled to a common terminal 20 for receiving a common voltage GND, and a gate 16 for receiving the input voltage V.sub.IN.
In parallel with the N-channel transistor MN1 is a second diode-connected transistor MN2. The diode-connected transistor MN2 has a gate and a drain that are tied together that are connected to the drain of P-channel transistor MP1. Diode-connected transistor MN2 also has a source coupled to the common terminal 20. The gate-drain connection of transistor MN2 is connected to an output terminal 18 for providing the output voltage signal V.sub.OUT.
The resulting constant current logic gate 30 is so called because it constantly conducts static current, regardless of the state of V.sub.IN. This is seen by considering the possible voltage levels on the input voltage V.sub.IN. Under normal operating conditions, the bias voltage V.sub.BIAS is set to a predetermined voltage level to bias the P-channel transistor MP1 in order to conduct a predetermined amount of constant current. The input voltage V.sub.IN, on the other hand, toggles between a first and a second voltage level or state.
In the first state, the input voltage level is insufficient to turn N-channel FET MN 1 on. The first state occurs when the input voltage V.sub.IN is less than the threshold voltage V.sub.T of MN1. With the N-channel transistor MN1 turned off all of the current flows through the diode-connected transistor MN2. The output voltage VOUT is at a level high and has an amplitude described by the following equation: EQU VOUT=(2.times.I/[K.times.W/L])0.5+V.sub.t
Where:
I=current sourced through MN2; PA1 K=dielectric constant; PA1 W=gate width; and PA1 L=gate length.
In the second state, N-channel transistor MN1 is turned on and, thus, the output voltage V.sub.OUT is equal to the drain-to-source voltage of MN1. The drain to source voltage, however, is nearly zero depending on how far the input voltage is above the threshold voltage V.sub.T. The drain-to-source voltage is insufficient to allow the diode-connected transistor MN2 to conduct current. As a result, all of the current is conducted through the N-channel transistor MN 1.
The constant current logic gate 30 is the logical equivalent of the inverter 10 of FIG. 1. Moreover, logic gate 30 provides lower electromagnetic emissions than its CMOS counterpart. However, unlike inverter 10, the constant current logic gate 30 has a DC current path regardless of the state of the input voltage V.sub.IN. Therefore, static current testing of gate 30 cannot be performed.
As the input voltage signal transitions between either of the two states there is a slight perturbation in the current as it is diverted from one transistor to the other. The magnitude of the perturbation, however, is substantially less than the noise spike produced by the inverter of FIG. 1. Thus, the corresponding voltage drop produced by the inductive component of the supply conductor is reduced proportionately. The improved noise characteristics make constant current logic superior to typical CMOS in low noise applications. However, because of the constant bias current, static current testing cannot be performed on constant current logic without disabling the bias current.
A similar constant current logic gate can be constructed for a differential input signal, as shown in FIG. 4. The logic gate shown in FIG. 4 is commonly referred to as folded source coupled logic (FSCL). The FSCL gate 35 includes two constant current logic gates arranged in a symmetrical, differential configuration. The first half includes current source transistor MP2, input transistor MN3, and diode-connected transistor MN4. The second half consists of current source MP3, input transistor MN5, and diode-connected transistor MN6. Unlike the constant-current logic gate 30 the input transistors MN3 and MN5 of FSCL gate 35 are coupled to a second N-channel current source MN7. Current sources MP2 and MP3 are biased by a first bias voltage V.sub.B1. The second current source MN7 is biased by a separate bias voltage V.sub.B2.
Each half of FSCL gate 35 operates in substantially the same manner as constant current logic gate 30. Either the diode-connected transistor is conducting current or the corresponding input transistor is conducting current produced by the corresponding P-channel current source, i.e., MP2 or MP3. Unlike the single-ended, constant current logic gate 30, however, the gates of input transistors MN3 and MN5 are driven by opposite polarity signals IN and IN in a differential manner. Thus, as is apparent to one skilled in the art, either MN3 or MN5 are conducting, but not both. Therefore, differential output terminals 40 and 42 are at opposite polarites to each other to produce an inverted differential output OUT and/OUT.
The FSCL gate 35 also demonstrates the same low noise characteristics as does the constant current logic gate 30. It accomplishes this in the same manner as the constant current logic gate 30 by "steering" the current from one path to another without substantially changing the magnitude of the current. Like the constant current gate static current testing cannot be performed on FSCL gate 35 because of the DC path that exists in all input states. Accordingly, a need remains for static current testing of constant current logic families.